1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and more particularly to a semiconductor memory device equipped with a timing control circuit that simulates a signal delay.
2. Description of the Related Art
It is required to finely control the operation timing of a semiconductor memory device to speed up the operation thereof. An attempt to realize a finer structure of the memory device by the fabrication process would result in an increased trend towards an unevenness of performance over the devices caused by a factor related to the fabrication process. It would be very difficult to perform fine timing control of the devices having dispersion in the performance.
For example, it is known to employ a delay circuit or a chopper circuit, which generates, from an external signal, a timing control signal that defines the operation timings of internal circuits of a semiconductor memory device. However, dispersion of the load capacitance or parasitic capacitance coupled to a wiring line would cause the timing control signal to deviate from the target timing. This requires the timing settings taken into consideration the deviation of the timing control signal. This prevents the speedup of the semiconductor memory device.
In order to overcome the above problem, Japanese Laid-Open Patent Application No. 11-203877 discloses the use of a circuit that simulates a signal delay caused in a route that has the greatest delay of time in terms of memory access. The simulation circuit is used to generate a timing control signal that defines the operation timings of the internal circuits. The timing control signal thus generated simulates the timings of the real memory access, so that unevenness of performance introduced during the fabrication process can be absorbed to some extent.
It is to be noted that the proposal disclosed in Japanese Laid-Open Patent Application No. 11-203877 employs the route that is furthest away from the input/output circuit of the memory device and is used to access the furthest memory cell from the row decoder. The following problems would arise from the use of the furthest route, as described below.
FIG. 1 is a view that explains an operation timing that takes place when the route that is furthest away from an input/output circuit and a row decoder is used for timing compensation.
A semiconductor memory device shown in FIG. 1 includes a clock generator part 10, a row decoder part 11, a sense amplifier/input-output circuit part 12, a timing control signal generating part 13, and a memory array part 14. FIG. 1 shows how the timing control is performed when data located close to the center illustrated by a dotted line AAxe2x80x2 is read.
The clock generator part 10 generates, from an external clock supplied from the outside of the semiconductor memory device, an internal clock that controls internal operations of the device. A pulse signal based on the internal clock travels a distance Yc over a signal line along the row decoder part 11. Then, the pulse signal travels a distance Xc over a signal line as a word line activating signal of a row decoder in the row decoder part 11. An access to a memory cell located in an upper right position is simulated, and a pulse signal that simulates data travels distance Yc along a signal line that simulates a bit line, and arrives at the sense amplifier/input-output circuit part 12. Then, the pulse signal travels distance Xc along the signal line, and arrives at the timing control signal generating part 13. The part 13 generates, from the received pulse signal propagated along the above route, a timing control signal that controls the operation timings of a data output circuit in the sense amplifier/input-output circuit part 12. The timing control signal travels over a signal line of a length Xc/2, and is supplied to the data output circuit, which latches output data in response to the timing control signal. The data latched in the data output circuit is propagated along a signal route having a length Yio, and is output to the outside of the memory device.
Hence, the time it takes for the data output circuit to latch, in response to the timing signal, data that is located close to the center AAxe2x80x2 and is propagated to the data output circuit can be expressed as follows:
Yc+Xc+Yc+Xc+(Xc/2).
By way of another example, data that is located in an upper portion of the central line of the memory array part 14 is read therefrom and is propagated to finally arrive at the data output circuit as follows. An address signal based on the timing of the internal clock travels distance Yc over the signal line along the row decoder part 11. Then, a corresponding row decoder of the row decoder part 11 is decoded into a word line activating signal, which travels distance Xc/2 along the word line. Thus, a memory cell located in an upper position on the central line of the memory array part 14 is accessed. A data signal from the memory cell travels distance Yc along the bit line, and arrives at the sense amplifier/input-output circuit part 12. Thus, the time of arrival from the initial timing can be expressed as follows:
Yc+(Xc/2)+Yc.
Thus, there is a difference of 2Xc between the timing when the data output circuit latches data in response to the timing control signal and the timing when the data arrives as the data output circuit.
When a memory cell located in an upper left position of the memory array part 14 is accessed, the data output circuit latches data in response to the timing control signal at a timing described below:
Yc+Xc+Yc+Xc
and the data arrives at the data output circuit at a timing described below:
Yc+Yc.
Thus, the difference between the latch timing and the arrival timing is also equal to 2Xc.
When a memory cell located in an upper right position of the memory array part 14 is accessed, the data output circuit latches data in response to the timing control signal at a timing described below:
Yc+Xc+Yc+Xc+Xc
and the data arrives at the data output circuit at a timing described below:
Yc+Xc+Yc.
Thus, the difference between the latch timing and the arrival timing is also equal to Xc.
It can be seen from the above that a needless wiring delay of 2Xc is constantly included when the timing compensation is performed using the route shown in FIG. 1. However, the wiring delay of 2Xc is too much to speed up the circuit operation.
With the above in mind, it would be conceivable to employ a route shown in FIG. 2 to perform timing compensation. The timing control signal generating part 13 is provided at the right side of the sense amplifier/input-output circuit part 12 with regard to the route shown in FIG. 2.
When a memory cell located in an upper position on the central line of the memory array part 14 is accessed, the data output circuit latches data in response to the timing control signal at a timing described below:
Yc+Xc+Yc+Xc/2
and the data arrives at the data output circuit at a timing described below:
Yc+Xc/2+Yc.
Thus, the difference between the latch timing and the arrival timing is also equal to 2Xc.
When a memory cell located in an upper left position of the memory array part 14 is accessed, the data output circuit latches data in response to the timing control signal at a timing described below:
xe2x80x83Yc+Xc+Yc+Xc
and the data arrives at the data output circuit at a timing described below:
Yc+Yc.
Thus, the difference between the latch timing and the arrival timing is also equal to 2Xc.
When a memory cell located in an upper right position of the memory array part 14 is accessed, the data output circuit latches data in response to the timing control signal at a timing described below:
Yc+Xc+Yc
and the data arrives at the data output circuit at a timing described below:
Yc+Xc+Yc.
Thus, the difference between the latch timing and the arrival timing is zero.
As described above, the timing compensation with the route shown in FIG. 2 results in a maximum wiring delay of 2Xc and a minimum wiring delay of zero. Thus, the above method would not cope with an error of the delay time caused by a factor involved in the fabrication process at all. Hence, it is necessary to ensure a somewhat margin taking the delay time equal to zero into consideration. This requires a delay of time equal to or longer than 2Xc when the maximum delay time is considered. Therefore, it is not expected that the circuit operates at a high speed and in a stable fashion because the margin is not much for the wiring delay of zero.
It is a general object of the present invention to provide a semiconductor memory device in which the above disadvantages are eliminated.
A more specific object of the present invention is to provide a semiconductor memory device capable of operating at a high speed and in a stable fashion regardless of unevenness of performance over devices introduced during the fabrication process.
The above objects of the present invention are achieved by a semiconductor memory device comprising: a row decoder selecting a row; word lines that extend from the row decoder and are connected to memory cells; a dummy word line that extends from starting ends of the word lines substantially in parallel therewith and returns to the starting ends in which the dummy word line is folded back in a predetermined position of a total length of the word lines; and a sense amplifier that amplifies data read from a memory cell coupled to a selected one of the word lines at a timing defined by a signal propagated along the dummy word line.
The above objects of the present invention are also achieved by a semiconductor memory device comprising: a timing control signal generating circuit that simulates a data access route to a memory cell and thus generates a timing control signal; and a dummy word line that extends substantially in parallel with word lines and returns to starting ends of the word lines in a predetermined position of a total length of the word lines, the timing control signal generating circuit generating a timing control signal based on a signal propagated along the dummy word line.